Home › Sessions

Themes & Sessions

Focused Sessions for Designers, Researchers & Builders

The program is organised into practical, outcome-oriented Sessions that span the full open hardware stack – from RTL to silicon, and from research ideas to products.

Learning Flow

Outcome Checklist

Key skills students gain during the full program


  • ✔ Ability to log in via RDP
  • ✔ Clear understanding of how RTL is transformed into GDSII
  • ✔ Capability to interpret VLSI layout
  • ✔ Strong understanding of DRC / LVS / STA
  • ✔ Competence to run OpenLane on a personal laptop or remote server
  • ✔ Readiness to deliver a complete ASIC flow for a small design
Session 1

Foundations

Lecture 30 min • Demo 30 min

Goal Introduce OpenLane, flow overview, PDK, RDP workflow
Topics Yosys, OpenROAD, Magic, Netgen, Docker setup
Commands / Files flow.tcl, directory layout, config.tcl, constraints.sdc
Checkpoint Students verify RDP connection and tool folders
Session 2

Prepare RTL

Lecture 20 min • Hands-on 40 min

Goal Write clean Verilog & minimal SDC; set up config.tcl
Topics Clock/reset, clean I/O, no X/Z, constraints basics
Files design/src/*.v, config.tcl
Checkpoint Yosys synthesis completes cleanly
Session 3

Run Full Flow

Stepwise vs Complete • Understanding logs

Goal Run synthesis → floorplan → placement → CTS → routing
Topics Yosys → ABC → DEF → LEF → OpenROAD logs
Commands ./flow.tcl -design <name>
Checkpoint Artifacts appear in runs/<tag>/
Session 4

Layout & Verification

Magic • KLayout • Netgen • OpenSTA

Goal Open layout, run DRC/LVS, run STA
Topics Magic DRC, Netgen LVS, STA timing reports
Commands magic -T sky130A.tech, netgen, openroad
Checkpoint DRC=0 or list of fixes, LVS matches
Session 5

GDSII Export

Export • Inspect • Mask layers

Goal Generate GDSII and inspect with KLayout
Topics Layers, vias, M1–M5, hierarchy
Commands magic -noconsole -dnull <<EOF
gds write design.gds
EOF
Checkpoint GDS opens cleanly in KLayout
Session 6

TYDI

Typed Streaming Interfaces for Hardware Systems

Goal Learn how to describe hardware streams using TYDI and generate clean interfaces
Topics Streams, packets, typed dataflow, TYDI specs, RTL generation, OpenLane integration
Commands / Files *.tydi.json, TYDI→HDL generator, RTL inspection
Checkpoint Student produces TYDI spec + generated RTL and verifies correctness
Session 7

Best Practices & Exercise

Debugging • Optimization • Q&A

Goal Students run full flow and fix issues
Topics Density, floorplan tweaks, antenna fixes, CTS tuning
Commands / Files config.tcl, constraints.sdc, re-run flow
Checkpoint Student produces a clean GDS + reports